Modern semiconductor fabrication involves numerous steps including photolithography, material deposition, and etching to form a plurality of individual semiconductor devices or integrated circuit chips (dies or dice) on a single semiconductor silicon wafer. Some of the individual chips formed on the wafer, however, may have defects due to variances and problems that may arise during the intricate semiconductor fabrication process. Prior to wafer dicing wherein the individual integrated circuit dies are separated from the semiconductor wafer, electrical performance and reliability tests are performed on a plurality of chips simultaneously by energizing them for a predetermined period of time (i.e., wafer level burn-in testing). These tests may typically include LVS (layout versus schematic) verification, IDDq testing, etc. The resulting electrical signals generated from each chip or DUT (device under test) are captured and analyzed by automatic test equipment (ATE) having test circuitry to determine if a chip has a defect.
To facilitate wafer level burn-in testing and electrical signal capture from numerous chips on the wafer at the same time, DUT boards or probe cards as they are commonly known in the art are used. Probe cards are essentially printed circuit boards (PCBs) that contain a plurality of metallic electrical probes that mate with a plurality of corresponding electrical contacts or terminal formed on the wafer for the semiconductor chips. Each chip or die has a plurality of contacts or terminals itself which must each be accessed for testing. A typical wafer level test will therefore require that electrical connection be made between well over 1,000 chip contacts or terminals and the ATE test circuitry. Accordingly, precisely aligning the multitude of probe card contacts with chip contacts on the wafer and forming sound electrical connections is important for conducting accurate wafer level testing. Probe cards are typically mounted in the ATE and serve as an interface between the chips (dies) or DUTs and the test head of the ATE.
As semiconductor fabrication technology advances continue to be implemented, the critical dimension or spacing between electrical test contact pads and bumps (i.e. “pitch”) on individual chips or dies formed on the semiconductor wafer continues to shrink. This makes it increasingly difficult to access these contacts properly for testing.
The present major trend in semiconductor fabrication is moving towards integration of 3D IC chip packages having vertically stacked chips and utilizing direct electrical inter-chip connections in lieu of other interconnect techniques such as wire bonds and chip edge interconnects. The dies in such 3D IC chip packages may include fine (small) pitch through substrate or silicon vias (TSVs) which are directly connected electrically to an adjoining stacked die. TSVs offer the possibility of higher density interconnects and shorter signal paths resulting in the possibility of forming die packages having smaller footprints. The TSVs in the dies may be terminated on the back side with very fine pitch microbump arrays for interconnection to adjacent stacked dies. The microbump arrays on the top die are also accessed for wafer level testing before the dies are assembled to a carrier substrate in the semiconductor device package. These microbump arrays may have a pitch (spacing) between the microbumps of 50 microns (μm) or less that must be accessed for die testing.
A technology bottleneck occurs that is associated with existing testing probe card designs and probing techniques that do not readily support testing such fine pitch microbump arrays encountered on dies that may be used in 3D IC chip packages. In some instances, direct probing of the microbumps by the test card probe tips may cause collapse or “crashing” of the microbumps as illustrated in FIG. 1 due to physical contact pressure and/or high current. This can result in permanent damage to the microbump, which adversely affects the integrity of the bump interconnect joint resulting in low bump joint yield and potential die rejection. In addition, the ability to properly access the fine pitch microbumps for testing is constrained by the larger pitch spacing of conventional testing card probe tips or needles as schematically illustrated in FIG. 2. All the die microbumps may therefore not be properly accessed for testing and signal transmission also resulting in low bump joint yield and die rejection.
An improved probing structure and method for fabricating the same is therefore desired for probing dies with microbump arrays.
All drawings are schematic and are not drawn to scale.